The present invention relates to a method for fabricating a semiconductor memory cell and particularly to a method to improve the overlay accuracy and to increase the storage capacitance of a capacitor by simultaneously etching a polysilicon pad and a polysilicon storage node using a self-alignment method.
FIGS. 1(A) through 1(F) show schematic views of a fabrication process for a semiconductor memory cell of a noble stacked capacitor structure according to the prior art.
The conventional process used in fabricating a semiconductor memory cell of a noble stacked capacitor structure is described below with reference to the several views of FIG. 1:
As shown in FIG. 1(A), a gate 2 is formed on a substrate 1 and a CVD silicon oxide layer 3 is deposited using a chemical vapor deposition process over the whole surface and is then etched to form a buried contact. Subsequently, a silicon nitride layer 4 for a mask is deposited and patterned.
Thereafter, as shown in FIG. 1(B), a polysilicon layer is deposited on the whole surface and patterned to form polysilicon pad 5. As shown in FIG. 1(C), a silicon oxide layer 6 is deposited by using a CVD method and is patterned and then a polysilicon layer 7 is formed on the whole surface by using a CVD method.
Next, as shown in FIG. 1(D), said polysilicon layer 7 is etched by using an anisotropic dry etching method to the deposition depth thereof and the silicon oxide layer 6 is removed to pattern a polysilicon storage node.
As shown in FIG. 1(E), a dielectric film 8 is formed and a polysilicon layer is deposited again and patterned to form the polysilicon plate 9. Therefore, the capacitor of a memory cell consisting of a polysilicon storage node, a dielectric film and a cell plate is fabricated. Finally, as shown in FIG. 1(F), an insulated layer 10 of Boron Phosphosilicate Glass (BPSG) is deposited, and etched to form contact and a tungsten plug 11 is next coated to form the bit line.
However, in the conventional technique used in fabricating a semiconductor memory cell of a noble stacked capacitor cell structure, the overlay accuracy is often inferior due to misalignment because of the need to etch both a polysilicon pad and a polysilicon storage node, and because the masking must also be accomplished in the fabrication process.